module dattet94
Title 'digital Attenuation Unit 4th edition '
Declarations
c384fs PIN;
lrin PIN;
datain PIN;
bckin PIN;
stin7..stin0 PIN;
dataout PIN istype 'com';
bckout PIN istype 'reg';
lrout PIN istype 'reg';
str7..str0 node istype 'reg';
auda15..auda0 PIN istype 'reg';
stda15..stda0 node istype 'reg';
count4..count0 node istype 'reg';
addr3..addr0 node istype 'reg';
outr3..outr0 node istype 'reg';
c1..c0 node istype 'reg';
m1..m0 node istype 'reg';
l3..l0 node istype 'reg';
addpa node;
mtlo = [l3..l0];
str = [str7..str0];
chklr = [c1..c0];
mprea = [m1..m0];
auda = [auda15..auda0];
stda = [stda15..stda0];
count = [count4..count0];
addr = [addr3..addr0];
outr = [outr3..outr0];
a = [0,0]; b = [0,1]; c = [1,0]; d = [1,1];
Equations
str.clk = c384fs; addr.clk = c384fs;
chklr.clk = c384fs; mprea.clk = c384fs;
mtlo.clk = c384fs; stda.clk = c384fs;
outr.clk = c384fs; bckout.clk = c384fs;
count.clk = c384fs; lrout.clk = c384fs;
[auda15..auda0].clk = bckin ;
[auda15..auda1] := [auda14..auda0];
auda0 := datain;
dataout = outr0;
state_diagram chklr
state 0: if lrin then 1 else 0;
state 1: if !lrin then 2 else 1;
state 2: goto 0;
state 3: goto 0;
state_diagram mprea
state a: if ((chklr==1) & (lrin==0)) then b else a;
state b: goto c ;
state c: if (mtlo!=9) then c
else if (count==31) then a else d;
state d: goto b;
equations
when ((mprea==b) # (mprea==c)) then
stda := stda;
else when ((mprea==d) & (count!=15)) then
stda := [stda15,stda15..stda1];
else
stda := auda;
when (mtlo!=9) then
lrout := lrout;
else
lrout := count4;
when (mtlo==3) then
bckout := 1;
else when (mtlo==9) then
bckout := 0;
else
bckout := bckout;
[outr3..outr1].clr = (mprea==a)
# ((mprea==d) & (count==15));
outr := addr & ((mtlo==9) & !([count3..count0]==0))
# addr & ((mtlo==9) & ([count3..count0]==0)) & (str==[0,0,0,0,0,0,0,1])
# [addr2..addr0,0] & ((mtlo==9) & ([count3..count0]==0)) & !(str==[0,0,0,0,0,0,0,1])
# outr & !(mtlo==9);
addpa = (mtlo==1) & stda0 & str0
# (mtlo==2) & stda1 & str1
# (mtlo==3) & stda2 & str2
# (mtlo==4) & stda3 & str3
# (mtlo==5) & stda4 & str4
# (mtlo==6) & stda5 & str5
# (mtlo==7) & stda6 & str6
# (mtlo==8) & stda7 & str7;
state_diagram mtlo
state 0: addr := [0,outr3..outr1];
if (mprea==c) then 1 else 0;
state 1: addr := addr + [0,0,0,addpa];
goto 2;
state 2: addr := addr + [0,0,0,addpa];
goto 3;
state 3: addr := addr + [0,0,0,addpa];
goto 4;
state 4: addr := addr + [0,0,0,addpa];
goto 5;
state 5: addr := addr + [0,0,0,addpa];
goto 6;
state 6: addr := addr + [0,0,0,addpa];
goto 7;
state 7: addr := addr + [0,0,0,addpa];
goto 8;
state 8: addr := addr + [0,0,0,addpa];
goto 9;
state 9: addr := addr;
goto 0;
state 10: goto 0;
state 11: goto 0;
state 12: goto 0;
state 13: goto 0;
state 14: goto 0;
state 15: goto 0;
equations
count := (count +1) & (mprea==d)
# (count) & ((mprea==b) # (mprea==c));
str := [stin7..stin0] & (mprea==a)
# str & !(mprea==a);
end dattet94
・・で、動かない版・・(爆)
module datte4
Title 'digital Attenuation Unit 4th edition '
Declarations
c384fs PIN;
lrin PIN;
datain PIN;
bckin PIN;
stin7..stin0 PIN;
dataout PIN istype 'com';
bckout PIN istype 'com';
lrout PIN istype 'reg';
auda15..auda0 PIN istype 'reg';
stda15..stda0 node istype 'reg';
addr3..addr0 node istype 'reg';
outr3..outr0 node istype 'reg';
count4..count0 node istype 'reg';
str7..str0 node istype 'reg';
str = [str7..str0];
c1..c0 node istype 'reg';
j2..j0 node istype 'reg';
s3..s0 node istype 'reg';
addpa node;
chklr = [c1..c0];
prim = [j2..j0];
sadd = [s3..s0];
auda = [auda15..auda0];
stda = [stda15..stda0];
addr = [addr3..addr0];
outr = [outr3..outr0];
count = [count4..count0];
Equations
chklr.clk = c384fs; prim.clk = c384fs;
sadd.clk = c384fs; str.clk = c384fs;
stda.clk = c384fs; addr.clk = c384fs;
outr.clk = c384fs; count.clk = c384fs;
lrout.clk = c384fs;
[auda15..auda0].clk = bckin ;
[auda15..auda1] := [auda14..auda0];
auda0 := datain;
dataout = outr0;
state_diagram chklr
state 0: if lrin then 1 else 0;
state 1: if !lrin then 2 else 1;
state 2: goto 0;
state 3: goto 0;
state_diagram j2
state 0: if ((!j1 & j0)
# (!j0 & ((chklr==1) & (lrin==0))))
then 1
else 0;
state 1: if (j0 & (sadd == 9)) then 0
else 1;
state_diagram j1
state 0: if (j2) then 1
else 0;
state 1: if (!j2) then 0
else 1;
state_diagram j0
state 0: if (j1 & (sadd == 4)) then 1
else 0;
state 1: if ((!j2 & (count == 0))
# (!j1 & j0)) then 0
else 1;
Equations
str := [stin7..stin0] & (prim==0)
# str & !(prim==0);
count.clr = !j2 & !j1 & !j0;
[outr3..outr1].clr = !j2 & !j1 & !j0;
when ([j1..j0] == [0,0]) then
count := count + 1;
else
count := count;
when (prim != [0,1,1]) then
outr := outr;
else when (count==1) then
outr := [addr2..addr0, 0];
else
outr := addr;
when (prim != [0,1,1]) then
lrout := lrout;
else when (count==1) then
lrout := 1;
else when (count==17) then
lrout := 0;
else
lrout := lrout;
bckout = j1 & j0;
when (j1 # j2) then
stda := stda;
else when (!j0) then
stda := auda;
else when (count==16) then
stda := auda;
else
[stda14..stda0] := [stda15..stda1];
stda15 := stda15;
addpa = (sadd==2) & stda0 & str0
# (sadd==3) & stda1 & str1
# (sadd==4) & stda2 & str2
# (sadd==5) & stda3 & str3
# (sadd==6) & stda4 & str4
# (sadd==7) & stda5 & str5
# (sadd==8) & stda6 & str6
# (sadd==9) & stda7 & str7;
state_diagram sadd
state 0: addr := addr;
if (prim == [1,0,0]) then 1;
else 0;
state 1: addr3 := 0;
[addr2..addr0] := [outr3..outr1];
goto 2;
state 2: addr := addr + [0,0,0,addpa];
goto 3;
state 3: addr := addr + [0,0,0,addpa];
goto 4;
state 4: addr := addr + [0,0,0,addpa];
goto 5;
state 5: addr := addr + [0,0,0,addpa];
goto 6;
state 6: addr := addr + [0,0,0,addpa];
goto 7;
state 7: addr := addr + [0,0,0,addpa];
goto 8;
state 8: addr := addr + [0,0,0,addpa];
goto 9;
state 9: addr := addr + [0,0,0,addpa];
goto 0;
end datte4
M-Tech design Inc. Digital Audio Attenuation Unit - ABEL Source - 
